1. Field of the Invention
The present invention relates to a receiving circuit of a signal transfer system and a semiconductor device in which the signal transfer system is applied, and more particular it relates to a receiving circuit of a signal transfer system performing signal transfer between LSI chips, between modules, and between a plurality of circuits within one and the same LSI chip, and to a semiconductor device in which this signal transfer system is applied.
2. Related Art
In recent years, there has been a demand for signal transfer with a high speed between, for example, a DRAM and a processor, or between circuits within a single semiconductor integrated circuit. The reason for this is that, with a dramatic improvement in the operating speed of CMOS LSI devices in recent years, microprocessors with clock frequencies exceeding 1 GHz being reported, the processing speed of equipment making use of these high-speed LSI devices has come to be restricted by the transfer speed between circuit boards, and between chips.
For example, in a personal computer in order to improve the signal processing speed from a DRAM to a processor, the improvement of the parallel transfer rate per pin to the gigabit level and beyond is being studied. In order to send such as high-speed signal outside the chip, it is necessary to take measures with respect to the significant deterioration of a signal waveform from the ideal transmitted signal waveform caused by attenuation and reflection in the transmission path, including the package and connectors.
FIG. 14 of the accompanying drawings shows a receiving end waveform of a signal transmitted on a transmission path. The transmitted signal undergoes multiple reflections along the transmission line and attenuation, the result being that a certain amount of time is required to reach the potential at the transmitting end. Given this situation, let us assume that the transmission path can be approximated by a circuit made up of lumped constants, in which the bit length of the transmitted signal is T, and the time constant of the transmission line is xcfx84. In the example shown in the drawing, the bit length T is shorter than the time constant of the transmission path (T less than xcfx84), in response to data changes (time slot xe2x80x9cnxe2x80x9d), data undergoes a new change (time slot xe2x80x9cn+1) at time T during which the signal voltage at the receiving end is changing. If the potential at the time n+1 is V(n+1) and the potential at the time n is V(n), because the potential change can be expressed by the relationship V(n+1)=V(n) (1xe2x88x92exp(xe2x88x92T/xcfx84)), in the case in which the time constant of the transmission path is longer than the bit length of the transmitted signal, it can be seen that there is a large change in the signal at the receiving end because of the influence of the past logic state of the signal. In particular in the case in which the transmitted signal remains at the 0 or 1 state continuously, with a subsequent single-bit reversal to the other logic state, the received signal does not reach a logic signal level enabling sufficient discrimination by a discrimination circuit, thereby resulting in an erroneous judgment by the discriminating circuit.
In order to solve such problems, one method is to simply use a transmission medium having superior high-frequency characteristics. Such a transmission medium, however, generally not only has a high cost, but also requires a large amount of mounting space, thereby resulting in the problem of an increased size of the system. As shown in the Japanese unexamined patent publication (KOKAI) No.10-275038, the Japanese Utility Model (KOKOKU) No.5-46366 and IECE C-II, Vol. J82-C-II, No. 5 pp. 239-246, there is a method of storing the past signal states in shift registers or the like, and applying weighting to these information to change the level of a reference signal. The circuit configuration in disclosed in the above-mentioned IECE C-II, Vol. J82-C-II, No. 5 pp. 239-246 is shown in FIG. 15. Because the results of a judgment made by the first latch stage of the receiving circuit are successively stored into a shift register, the each output bit of the shift register represents the past received signal. In the example shown in the drawing, a 2-bit shift register 26 is used to store past signal information, this information being used for changing the level of a reference signal, using a D/A converter 23 to act as a weighting circuit. The first latch stage of the shift register has a differential circuit configuration that performs a comparison with a reference signal and a received signal, to be described later, and the output of this latch circuit is the output of the receiving circuit. The weighting circuit in this example is a circuit which outputs an average value of a plurality of signals.
To simplify the description of the operation of the circuit of FIG. 15, consider the case in which signal information for the immediately previous two bits is not weighted. In this case, if the two bit previous signals and one bit previous signal are both at the 0 level, the weighting circuit outputs a low level as the reference potential. If the either one of two bit previous signals and one bit previous signal is at the 1 level and the other is at the 0 level, the reference potential would be an intermediate potential, and if the two bits previous signals and one bit previous signal are both at the 1 level, the reference potential would be at the high level.
FIG. 16 of the accompanying drawings shows the signal waveform at the receiving end, the logic discrimination reference voltage of this circuit, the logic value at the transmitting end, and the logic value judged by this circuit, for the case in which the data period T is 0.5xcfx84. It can be seen that, although the signal waveform is considerably deteriorated at the receiving end, because the reference signal used for logic discrimination is set to the average value of a past data series, a potential appropriate for logic discrimination is achieved, making it possible to receive the signal without erroneous logic level discrimination. In this drawing, the potential in which the reference voltage is constant is shown. The white characters on black background in FIG. 16 indicates erroneous discrimination.
In the example of this circuit, the change in level of the reference signal is 1/4 of the signal amplitude, and in the case of a transmission medium having poor frequency characteristics, it is necessary to adjust for an even narrower signal level. To make a finer signal adjustment, it is necessary to increase the number of level shift register stages and input each output bit thereof to a weighting circuit. For example, in the case of using a 3-bit shift register, it is possible to establish 5 levels of reference potential.
Using this method, there is the drawback that, if the number of shift register stages is made large and the reference signal level is controlled even more finely, if even one erroneous discrimination occurs, this erroneous discrimination will continue for a long period.
In order to avoid this problem, a configuration as shown in FIG. 17 of the accompanying drawings has been proposed. This circuit uses two RZ signals, performs analog storage of the 1-bit previous signal level into a capacitor, and subtracts the 1-bit previous signal level from the current signal level, so as to eliminate the influence of the past signal, and it performs logic level discrimination. The operation of this circuit is described below, with reference made to FIG. 17.
In the case in which the clock signal xcfx861 is at a high level, the input voltage Vnxe2x88x921 in the receiving circuit at the time xe2x80x9cnxe2x88x921xe2x80x9d and the reference potential VTT are received by the capacitors C1 and C2, simultaneously with which the input and output of an inverter are shorted (FIG. 17 (a)). The output potential of the inverter with the input and output thereof shorted is the logic threshold of that inverter. Next, in the case in which xcfx862 is at the high level, the input voltage Vn at the time n is sampled via the capacitors C1 and C2 (FIG. 17 (b)). If these capacitances of the capacitors C1 and C2 are set so that C1/(C1+C2)=exp(xe2x88x92T/xcfx84), the voltage appearing across the parallel capacitance of C1 and C2 is a voltage that corresponds to the influence of the past signal. Because these capacitors are provided in series with the input of the receiving circuit inverter, the automatic subtraction operation is performed, even if there is only a very small change in signal potential at the receiving end of the transmission path, thereby it is possible to perform accurate logic discrimination.
FIG. 18 of the accompanying drawings shows the signal waveform at the receiving end, the logic discrimination reference voltage of this partial response detector circuit (PRD), the logic value at the transmitting end, and the logic value judged by this circuit, for the case in which the data period T is 0.5xcfx84. It can be seen that, although the signal waveform is considerably deteriorated at the receiving end, because the reference signal used for logic discrimination is set to an intermediate value between the 1 bit previous signal and the current signal potential, it is possible to receive the signal without erroneous logic level discrimination.
In a system that stores a potential level in a capacitance so as to cause the generation of an ideal reference potential as described above, it is necessary to have a high-speed RZ signal, and the RZ signal generation circuit becomes the governing factor in determining the overall speed of the LSI device. Accordingly, it is necessary to use basic elements having high-frequency characteristics. Additionally, because variation in the capacitance values formed as part of the LSI device directly influences the logic discrimination reference potential, precise control for fabricating of this capacitance is required.
Accordingly, it is an object of the present invention to solve the above-described drawbacks in the related art, by providing a novel receiving circuit using relatively little past data, such as 1 or 2 bits, capable of generating a reference potential with a simple clock signal.
To achieve the above-noted objects, the present invention adopts the following described technical constitution.
The first aspect of the present invention is a receiving circuit for receiving a signal transmitted to a signal transmission path, the receiving circuit comprising: a signal potential detection means for detecting signal potential of the received signal, a signal logic value discrimination means for discriminating a logic value of the received signal, and a reference signal generation means for generating a reference signal for the signal logic value discrimination means, based on a signal potential detected by the signal potential detection means and a discrimination result of the signal logic value discrimination means.
The second aspect of the present invention is that the signal logic value discrimination means comprising a comparator for comparing a potential of the received signal with that of the reference signal and for discriminating a level of the received signal.
The third aspect of the present invention is that the signal potential detection means holds discriminated logic levels of the received signal from a prescribed past time to the present time, and the reference signal generation means generates a reference potential of the reference signal for performing next logic discrimination of a received signal in the signal logic value discrimination means, based on data stored in the signal potential detection means.
The fourth aspect of the present invention is that the signal logic value discrimination means holds discriminated logic levels of the received signal from a prescribed past time to the present time, and the reference signal generation means generates a reference potential of the reference signal for performing next logic discrimination of a received signal, based on data stored in the signal logic value discrimination means.
The fifth aspect of the present invention is that the signal potential detection means holds detected signal levels of the received signal from a prescribed past time to the present time, and the signal logic value discrimination means holds discriminated logic levels of the received signal from a prescribed past time to the present time, the reference signal generation means generates a reference potential of the reference signal for performing next logic discrimination of a received signal in the signal logic value discrimination means, based on data stored in the signal potential detection means and the signal logic value discrimination means.
The sixth aspect of the present invention is that the signal logic value discrimination means comprising a comparator for comparing the received signal with the reference signal, and a first flip-flop circuit for latching comparison results thereof, the signal potential detection means comprising a comparator for comparing the received signal with a fixed potential, and a second flip-flop circuit for latching comparison results thereof, and the reference signal generation means comprising a D/A converter for applying weighting to signals output from the first flip-flop circuit and the second flip-flop circuit, and generating a reference potential of the reference signal.
The seventh aspect of the present invention is that the signal logic value discrimination means comprising a comparator for comparing the received signal with the reference signal, and at least one shift register connected to the first comparator, the signal potential detection means comprising a comparator for comparing the received signal with a fixed potential, and a flip-flop circuit for latching comparison results thereof, and the reference signal generation means comprising a D/A converter for applying weighting to signals output from the shift register and the flip-flop circuit, and generating a reference potential of the reference signal.
The eighth aspect of the present invention is that the signal logic value discrimination means comprising a comparator for comparing the received signal with the reference signal, a first flip-flop circuit for latching comparison results thereof, and a plurality of shift registers connected in series to the first flip-flop circuit, the signal potential detection means comprising a comparator for comparing the received signal with a prescribed potential, and a second flip-flop circuit for latching comparison results thereof, and the reference signal generation means comprising a D/A converter for applying weighting to signals output from the shift registers and the second flip-flop circuit, and generating a reference potential of the reference signal.
The ninth aspect of the present invention is that the signal logic value discrimination means comprising a comparator for comparing the received signal with the reference signal, and a flip-flop circuit for latching comparison results thereof, the signal potential detection means comprising an A/D converter for detecting a level of the received signal, and the reference signal generation means comprising an D/A converter for applying weighting to the signal detected by the A/D converter and generating a reference potential of the reference signal.
The tenth aspect of the present invention is that the signal logic value discrimination means comprising a comparator for comparing the received signal with the reference signal, and a first flip-flop circuit for latching comparison results thereof, the signal potential detection means comprising a plurality of prescribed potentials which are different each other, a plurality of comparator for comparing the received signal with the fixed potential, and a plurality of second flip-flop circuits for latching each of the comparison results, and the reference signal generation means comprising a D/A converter for applying weighting to signals output from the first flip-flop circuit and the second flip-flop circuits and generating a reference potential of the reference signal.
The eleventh aspect of the present invention is that a step width of the reference signal is established to be fine in the vicinity of a center point of an amplitude of the received signal in a full swing condition, and the step width is established to be widened in directions of a lowest value and a highest value.
The twelfth aspect of the present invention is that, if a step width of the reference signal is xcex94V, a number of steps of the reference signal is M, discrimination level of each step is VTH(n) (1 less than n=Mxe2x88x921), a time constant in a case of approximating the signal transmission path with a lumped constant is xcfx84, a data bit length is T, and an amplitude of the received signal in a full-swing condition is Vfullsw, the step width xcex94V and each discrimination level VTH (n) satisfy the following condition, xcex94V less than Min. [(Vfullswxe2x88x92VTH(n)) (1xe2x88x92exp(xe2x88x92T/xcfx84)),VTH (n) (1xe2x88x92exp(xe2x88x92T/xcfx84))].